View 83L51FA_1956592.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

* other brands and names are the property of their respective owners. information in this document is provided in connection with intel products. intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of intel products except as provided in intel's terms and conditions of sale for such products. intel retains the right to make changes to these specifications at any time, without notice. microcomputer products may have minor variations to this specification known as errata. november 1994 copyright ? intel corporation, 1995 order number: 272356-003 8xl51fa/fb/fc low voltage chmos single-chip 8-bit microcontrollers commercial/express 87l51fa/83L51FA/80l51fa/87l51fb/83l51fb/87l51fc/83l51fc y high performance chmos otp rom/ rom/cpu y low voltage operation y 20 mhz commercial/16 mhz express operation y three 16-bit timer/counters y programmable counter array with: e high speed output, e compare/capture, e pulse width modulator, e watchdog timer capabilities y up/down timer/counter y three level program lock system y 8k/16k/32k on-chip program memory y 256 bytes of on-chip data ram y improved quick pulse programming algorithm y boolean processor y 32 programmable i/o lines y 7 interrupt sources y four level interrupt priority y programmable serial channel with: e framing error detection e automatic address recognition y 64k external program memory space y 64k external data memory space y mcs 51 microcontroller compatible instruction set y power saving idle and power down modes y once (on-circuit emulation) mode y extended temperature range ( b 40 cto a 85 c) memory organization device rom otp rom version romless version rom/ bytes ram otp rom bytes 83L51FA 87l51fa 80l51fa 8k 256 83l51fb 87l51fb 80l51fa 16k 256 83l51fc 87l51fc 80l51fa 32k 256 these devices can address up to 64 kbytes of external program/data memory. the intel 8xl51fa/8xl51fb/8xl51fc is a single-chip control oriented microcontroller which is fabricated on intel's reliable chmos iii-e technology. being a member of the mcs 51 microcontroller family, the 8xl51fa/8xl51fb/8xl51fc uses the same powerful instruction set, has the same architecture, and is pin- for-pin compatible with the existing mcs 51 microcontroller products. the 8xl51fx is a 3v version of current 8xc51fx and will operate from 2.7v to 3.6v at a frequency range of 3.5 mhz to 16 mhz (express)/20 mhz (commercial). for the remainder of this document, the 8xl51fa, 8xl51fb, 8xl51fc will be referred to as the 8xl51fx, unless information applies to a specific device.
8xl51fa/fb/fc standard b 1 b 20 * 80l51fa x x x 83L51FA x x x 87l51fa x x x 83l51fb x x x 87l51fb x x x 83l51fc x x x 87l51fc x x x note: standard 3.5 mhz to 12 mhz; 2.7v to 3.6v b 1 3.5 mhz to 16 mhz; 2.7v to 3.6v b 20 * 3.5 mhz to 20 mhz; 2.7v to 3.6v * only available for commercial standard temperature range, not available at express temperature range. 272356 1 figure 1. 8xl51fx block diagram 2
8xl51fa/fb/fc process information the 8xl51fa/8xl51fb/8xl51fc is manufactured on p629.5, a chmos iii-e process. additional pro- cess and reliability information is available in intel's components quality and reliability handbook, or- der number 210997. packages part prefix package type 8xl51fx n 44-pin plcc (otp) s 44-pin qfp (otp) 272356 2 plcc 272356 3 qfp figure 2. pin connections 3
8xl51fa/fb/fc pin descriptions v cc : supply voltage. v ss : circuit ground. port 0: port 0 is an 8-bit, open drain, bidirectional i/o port. as an output port each pin can sink several inputs. port 0 pins that have 1's written to them float, and in that state can be used as high-impedance inputs. port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. in this application it uses strong inter- nal pullups when emitting 1's, and can source and sink several inputs. port 0 also receives the code bytes during otp rom programming, and outputs the code bytes dur- ing program verification. external pullup resistors are required during program verification. port 1: port 1 is an 8-bit bidirectional i/o port with internal pullups. the port 1 output buffers can drive several inputs. port 1 pins that have 1's written to them are pulled high by the internal pullups, and in that state can be used as inputs. as inputs, port 1 pins that are externally pulled low will source current (i il , on the data sheet) because of the internal pull- ups. in addition, port 1 serves the functions of the follow- ing special features of the 8xl51fx: port pin alternate function p1.0 t2 (external count input to timer/ counter 2), clock out p1.1 t2ex (timer/counter 2 capture/ reload trigger and direction control) p1.2 eci (external count input to the pca) p1.3 cex0 (external i/o for compare/ capture module 0) p1.4 cex1 (external i/o for compare/ capture module 1) p1.5 cex2 (external i/o for compare/ capture module 2) p1.6 cex3 (external i/o for compare/ capture module 3) p1.7 cex4 (external i/o for compare/ capture module 4) port 1 receives the low-order address bytes during otp rom programming and verifying. port 2: port 2 is an 8-bit bidirectional i/o port with internal pullups. the port 2 output buffers can drive several inputs. port 2 pins that have 1's written to them are pulled high by the internal pullups, and in that state can be used as inputs. as inputs, port 2 pins that are externally pulled low will source current (i il , on the data sheet) because of the internal pull- ups. port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (movx @ dptr). in this application it uses strong internal pullups when emitting 1's. dur- ing accesses to external data memory that use 8-bit addresses (movx @ ri), port 2 emits the contents of the p2 special function register. some port 2 pins receive the high-order address bits during otp rom programming and program verifi- cation. port 3: port 3 is an 8-bit bidirectional i/o port with internal pullups. the port 3 output buffers can drive several inputs. port 3 pins that have 1's written to them are pulled high by the internal pullups, and in that state can be used as inputs. as inputs, port 3 pins that are externally pulled low will source current (i il , on the data sheet) because of the pullups. port 3 also serves the functions of various special features of the mcs 51 microcontroller family, as listed below: port pin alternate function p3.0 rxd (serial input port) p3.1 txd (serial output port) p3.2 int0 (external interrupt 0) p3.3 int1 (external interrupt 1) p3.4 t0 (timer 0 external input) p3.5 t1 (timer 1 external input) p3.6 wr (external data memory write strobe) p3.7 rd (external data memory read strobe) rst: reset input. a high on this pin for two machine cycles while the oscillator is running resets the de- vice. the port pins will be driven to their reset condi- tion when a minimum v ih2 voltage is applied wheth- er the oscillator is running or not. an internal pull- down resistor permits a power-on reset with only a capacitor connected to v cc . 4
8xl51fa/fb/fc ale: address latch enable output pulse for latching the low byte of the address during accesses to ex- ternal memory. this pin (ale/prog ) is also the program pulse input during otp rom programming for the 87l51fx. in normal operation ale is emitted at a constant rate of (/6 the oscillator frequency, and may be used for external timing or clocking purposes. note, how- ever, that one ale pulse is skipped during each ac- cess to external data memory. if desired, ale operation can be disabled by setting bit 0 of sfr location 8eh. with this bit set, the pin is weakly pulled high. however, the ale disable fea- ture will be suspended during a movx or movc in- struction, idle mode, power down mode and ice mode. the ale disable feature will be terminated by reset. when the ale disable feature is suspended or terminated, the ale pin will no longer be pulled up weakly. setting the ale-disable bit has no affect if the microcontroller is in external execution mode. throughout the remainder of this data sheet, ale will refer to the signal coming out of the ale/prog pin, and the pin will be referred to as the ale/prog pin. psen : program store enable is the read strobe to external program memory. when the 8xl51fx is executing code from external program memory, psen is activated twice each ma- chine cycle, except that two psen activations are skipped during each access to external data memo- ry. ea /v pp : external access enable. ea must be strapped to vss in order to enable the device to fetch code from external program memory locations 0000h to 0fffh. note, however, that if either of the program lock bits are programmed, ea will be inter- nally latched on reset. ea must be strapped to v cc for internal program executions. this pin also receives the programming supply volt- age (v pp ) during otp rom programming. xtal1: input to the inverting oscillator amplifier. xtal2: output from the inverting oscillator amplifier. oscillator characteristics xtal1 and xtal2 are the input and output, respec- tively, of a inverting amplifier which can be config- ured for use as an on-chip oscillator, as shown in figure 3. either a quartz crystal or ceramic resonator may be used. more detailed information concerning the use of the on-chip oscillator is available in appli- cation note ap-155, ``oscillators for microcontrol- lers.'' to drive the device from an external clock source, xtal1 should be driven, while xtal2 floats, as shown in figure 4. there are no requirements on the duty cycle of the external clock signal, since the in- put to the internal clocking circuitry is through a di- vide-by-two flip-flop, but minimum and maximum high and low times specified on the data sheet must be observed. an external oscillator may encounter as much as a 100 pf load at xtal1 when it starts up. this is due to interaction between the amplifier and its feedback capacitance. once the external signal meets the v il and v ih specifications the capacitance will not ex- ceed 20 pf. 272356 4 c1, c2 e 30 pf g 10 pf for crystals for ceramic resonators, contact resonator manufacturer. figure 3. oscillator connections 272356 5 figure 4. external clock drive configuration idle mode the user's software can invoke the idle mode. when the microcontroller is in this mode, power consump- tion is reduced. the special function registers and the onboard ram retain their values during idle, but the processor stops executing instructions. idle mode will be exited if the chip is reset or if an en- abled interrupt occurs. the pca timer/counter can optionally be left running or paused during idle mode. 5
8xl51fa/fb/fc power down mode to save even more power, a power down mode can be invoked by software. in this mode, the oscillator is stopped and the instruction that invoked power down is the last instruction executed. the on-chip ram and special function registers retain their val- ues until the power down mode is terminated. on the 8xl51fx either hardware reset or external interrupt can cause an exit from power down. reset redefines all the sfrs but does not change the on- chip ram. an external interrupt allows both the sfrs and the on-chip ram to retain their values. to properly terminate power down the reset or ex- ternal interrupt should not be executed before v cc is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize (normally less than 10 ms). with an external interrupt, int0 or int1 must be en- abled and configured as level-sensitive. holding the pin low restarts the oscillator but bringing the pin back high completes the exit. once the interrupt is serviced, the next instruction to be executed after reti will be the one following the instruction that put the device into power down. design consideration # the 8xl51fx will operate from 2.7v to 3.6v with a frequency range of 3.5 mhz to 16 mhz (ex- press)/20 mhz (commercial). operating beyond these specifications could cause improper device functionality. # all v cc and v ss pins must be connected. please refer to figure 2, pin connections, for the specific pins. # when the idle mode is terminated by a hardware reset, the device normally resumes program exe- cution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. on-chip hardware inhibits access to inter- nal ram in this event, but access to the port pins is not inhibited. to eliminate the possibility of an unexpected write when idle is terminated by re- set, the instruction following the one that invokes idle should not be one that writes to a port pin or to external memory. once mode the once (``on-circuit emulation'') mode facilitates testing and debugging of systems using the 8xl51fx without the 8xl51fx having to be re- moved from the circuit. the once mode is invoked by: 1) pull ale low while the device is in reset and psen is high; 2) hold ale low as rst is deactivated. while the device is in once mode, the port 0 pins float, and the other port pins and ale and psen are weakly pulled high. the oscillator circuit remains ac- tive. while the 8xl51fx is in this mode, an emulator or test cpu can be used to drive the circuit. normal operation is restored when a normal reset is applied. table 1. status of the external pins during idle and power down mode program ale psen port0 port1 port2 port3 memory idle internal 1 1 data data data data idle external 1 1 float data address data power down internal 0 0 data data data data power down external 0 0 float data data data note: for more detailed information on the reduced power modes refer to current embedded microcontrollers and processors handbook volume i, y 270646, and application note ap-252 (embedded applications handbook), y 270648, ``designing with the 80c51bh.'' 6
8xl51fa/fb/fc 8xl51fx express the intel express system offers enhancements to the operational specifications of the mcs-51 family of microcontrollers. these express products are designed to meet the needs of those applications whose operating requirements exceed commercial standards. the express program includes the commercial standard temperature range with burn-in and an ex- tended temperature range with or without burn-in. with the commercial standard temperature range, operational characteristics are guaranteed over the temperature range of 0 cto70 c. with the extend- ed temperature range option, operational character- istics are guaranteed over the range of b 40 cto a 85 c. package types and express versions are identified by a one- or two-letter prefix to the part number. the prefixes are listed in table 2. for the extended temperature range option, this data sheet specifies the parameters which deviate from their commercial temperature range limits. table 2. prefix identification prefix package temperature type range n plcc commercial s qfp commercial tn plcc extended ts qfp extended note: contact your distributor or local sales office to match the express prefix with the proper device. examples: n87l51fc indicates 87l51fc in a plcc package and specified for commercial temperature range, without burn- in. tn87l51fc indicates 87l51fc in a plcc package and specified for extended temperature range with burn-in. 7
8xl51fa/fb/fc absolute maximum ratings * ambient temperature under bias b 40 cto a 85 c storage temperature b 65 cto a 150 c voltage on ea/v pp pin to v ss 0v to a 13.0v voltage on any other pin to v ss b 0.5v to a 6.5v i ol per i/o pin 15 ma power dissipation1.5w (based on package heat transfer limitations, not device power consumption) notice: this data sheet contains information on products in the sampling and initial production phases of development. it is valid for the devices indicated in the revision history. the specifications are subject to change without notice. * warning: stressing the device beyond the ``absolute maximum ratings'' may cause permanent damage. these are stress ratings only. operation beyond the ``operating conditions'' is not recommended and ex- tended exposure beyond the ``operating conditions'' may affect device reliability. operating conditions symbol description min max units t a ambient temperature under bias commercial 0 a 70 c express b 40 a 85 c v cc supply voltage 2.7 3.6 v dc characteristics (over operating conditions) all parameter values apply to all devices unless otherwise indicated. symbol parameter min max units test conditions v il input low voltage b 0.5 0.8 v (except xtal1, rst) v il1 input low voltage b 0.5 0.2 v cc b 0.1 v (xtal1, rst) v ih input high voltage 2.0 v cc a 0.5 v (except xtal1, rst, ea ) v ih1 input high voltage (ea )v cc b 1.0 v cc a 0.5 v v ih2 input high voltage 0.7 v cc v cc a 0.5 v (xtal1, rst) v ol output low voltage (note 4) 0.4 v i ol e 1.6 ma (note 1) (ports 1, 2 and 3) v ol1 output low voltage (note 4) 0.4 v i ol e 3.2 ma (port 0, ale/psen ) (note 1) v oh output high voltage v cc b 0.7 v i oh eb 30 m a (ports 1, 2 and 3, ale, psen (note 2) v oh1 output high voltage 2.4 v i oh eb 1.0 ma (port 0 in external bus mode) (note 2) i il logical 0 input current b 50 m av in e 0.4v (ports 1, 2 and 3) i li input leakage current (port 0) g 10 m a0 k v in k v cc 8
8xl51fa/fb/fc dc characteristics (over operating conditions) all parameter values apply to all devices unless otherwise indicated. (continued) symbol parameter min max units test conditions i tl logical 1 to 0 b 350 m av in e 1.4v transition current (ports 1, 2 and 3) rrst rst pulldown resistor 40 225 k x i cc power supply current (note 3) active mode at 16 mhz 25 ma idle mode at 16 mhz 8 ma power-down mode 30 m a notes: 1. capacitive loading on ports 0 and 2 may cause noise pulses above 0.4v to be superimposed on the v ol s of ale and ports 1, 2 and 3. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins change from 1 to 0. in applications where capacitance loading exceeds 100 pf, the noise pulses on these signals may exceed 0.8v. it may be desirable to qualify ale or other signals with a schmitt trigger, or cmos-level input logic. 2. capacitive loading on ports 0 and 2 cause the v oh on ale and psen to drop below the 0.9 v cc specification when the address lines are stabilizing. 3. see figures 6 9 for test conditions. minimum v cc for power down is 2v. 4. under steady state (non-transient) conditions, i ol must be externally limited as follows: maximum i ol per port pin: 10 ma maximum i ol per 8-bit port - port 0: 26 ma ports 1, 2, and 3: 15 ma maximum total i ol for all output pins: 71 ma if i ol exceeds the test condition, v ol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test conditions. running the device with ea at a higher voltage than v cc sinks additional currrent. 272356 6 i cc max at other frequencies (3.5 mhz to 20 mhz) is given by: active mode i cc max e 1.1 c freq a 7.6 idle mode i cc max e 0.4 c freq a 1.8 where freq is in mhz, i cc max is given in ma. figure 5. i cc vs frequency 9
8xl51fa/fb/fc 272356 7 all other pins disconnected tclch e tchcl e 5ns figure 6. i cc test condition, active mode 272356 8 all other pins disconnected tclch e tchcl e 5ns figure 7. i cc test condition idle mode 272356 9 all other pins disconnected figure 8. i cc test condition, power down mode. v cc e 2.7v to 3.6v. 272356 10 figure 9. clock signal waveform for i cc tests in active and idle modes. tclch e tchcl e 5 ns. 10
8xl51fa/fb/fc explanation of the ac symbols each timing symbol has 5 characters. the first char- acter is always a `t' (stands for time). the other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. the following is a list of all the characters and what they stand for. a: address c: clock d: input data h: logic level high i: instruction (program memory contents) l: logic level low, or ale p: psen q: output data r: rd signal t: time v: valid w: wr signal x: no longer a valid logic level z: float for example, tavll e time from address valid to ale low tllpl e time from ale low to psen low ac characteristics (over operating conditions, load capacitance for port 0, ale/prog and psen e 100 pf, load capacitance for all other outputs e 80 pf) external memory characteristics all parameter values apply to all devices unless otherwise indicated. in this table, 8xl51fx refers to 8xl51fx and 8xl51fx-1. symbol parameter 12 mhz 20 mhz variable units oscillator oscillator oscillator min max min max min max 1/tclcl oscillator frequency 8xl51fx 3.5 12 mhz 8xl51fx-1 3.5 16 mhz 8xl51fx-20 3.5 20 mhz tlhll ale pulse width 127 60 2 tclcl b 40 ns tavll address valid to 43 10 tclcl b 40 ns ale low tllax address hold after 53 20 tclcl b 30 ns ale low tlliv ale low to valid instruction in 8xl51fx 234 4 tclcl b 100 ns 8xl51fx-20 125 4 tclcl b 75 ns tllpl ale low to psen 53 20 tclcl b 30 ns low tplph psen pulse width 205 105 3 tclcl b 45 ns tpliv psen low to valid instruction in 8xl51fx 145 3 tclcl b 105 ns 8xl51fx-20 60 3 tclcl b 90 ns tpxix input instruction 0 0 0 ns hold after psen 11
8xl51fa/fb/fc external memory characteristics (continued) all parameter values apply to all devices unless otherwise indicated. symbol parameter 12 mhz 20 mhz variable units oscillator oscillator oscillator min max min max min max tpxiz input instruction float after psen 8xl51fx 59 tclcl b 25 ns 8xl51fx-20 30 tclcl b 20 ns taviv address to valid 312 145 5 tclcl b 105 ns instruction in tplaz psen low to address 10 10 10 ns float trlrh rd pulse width 400 200 6 tclcl b 100 ns twlwh wr pulse width 400 200 6 tclcl b 100 ns trldv rd low to valid data in 8xl51fx 252 5 tclcl b 165 ns 8xl51fx-20 155 5 tclcl b 95 ns trhdx data hold after rd 00 0 ns trhdz data float after rd 107 40 2 tclcl b 60 ns tlldv ale low to valid data in 8xl51fx 517 8 tclcl b 150 ns 8xl51fx-20 310 8 tclcl b 90 ns tavdv address to valid data in 8xl51fx 585 9 tclcl b 165 ns 8xl51fx-20 360 9 tclcl b 90 ns tllwl ale low to rd or wr 200 300 100 200 3 tclcl b 50 3 tclcl a 50 ns low tavwl address valid to wr low 8xl51fx 203 4 tclcl b 130 ns 8xl51fx-20 110 4 tclcl b 90 ns tqvwx data valid before wr 8xl51fx 33 tclcl b 50 ns 8xl51fx-20 15 tclcl b 35 ns twhqx data hold after wr 8xl51fx 33 tclcl b 50 ns 8xl51fx-20 10 tclcl b 40 ns tqvwh data valid to wr high 8xl51fx 433 7 tclcl b 150 ns 8xl51fx-20 280 7 tclcl b 70 ns trlaz rd low to address float 0 0 0 ns twhlh rd or wr high to ale 43 123 10 90 tclcl b 40 tclcl a 40 ns high 12
8xl51fa/fb/fc external program memory read cycle 272356 23 external data memory read cycle 272356 24 external data memory write cycle 272356 25 13
8xl51fa/fb/fc serial port timing - shift register mode test conditions: over operating conditions; load capacitance e 80 pf symbol parameter 12 mhz 20 mhz variable units oscillator oscillator oscillator min max min max min max txlxl serial port clock 1 0.600 12 tclcl m s cycle time tqvxh output data setup to 700 367 10 tclcl b 133 ns clock rising edge txhqx output data hold after clock rising edge 8xc5x 50 2 tclcl b 117 ns 8xc5x-20 50 2 tclcl b 50 ns txhdx input data hold after 0 0 0 ns clock rising edge txhdv clock rising edge to 700 367 10 tclcl b 133 ns input data valid shift register mode timing waveforms 272356 26 14
8xl51fa/fb/fc external clock drive symbol parameter min max units 1/tclcl oscillator frequency 8xl51fx 3.5 12 mhz 8xl51fx-1 3.5 16 8xl51fx-20 3.5 20 tchcx high time 20 ns tclcx low time 20 ns tclch rise time 20 ns tchcl fall time 20 ns external clock drive waveform 272356 27 ac testing input, output waveforms 272356 28 ac inputs during testing are driven at v cc b 0.5v for a logic ``1'' and 0.45v for a logic ``0''. timing measurements are made at v ih min for a logic ``1'' and v il max for a logic ``0''. float waveforms 272356 29 for timing purposes a port pin is no longer floating when a 100 mv change from load voltage occurs, and begins to float when a 100 mv change from the loaded v oh /v ol level occurs. i ol /i oh e g 20 ma (-l, i ol /i oh e g 10 ma). 15
8xl51fa/fb/fc programming the otp rom to be programmed, the part must be running with a 4 to 6 mhz oscillator. (the reason the oscillator needs to be running is that the internal bus is being used to transfer address and program data to appro- priate internal otp rom locations.) the address of an otp rom location to be programmed is applied to port 1 and pins p2.0 - p2.4 of port 2, while the code byte to be programmed into that location is applied to port 0. the other port 2 and 3 pins, rst psen , and ea /v pp should be held at the ``program'' levels indicated in table 3. ale/prog is pulsed low to program the code byte into the addressed otp rom location. the setup is shown in figure 10. normally ea /v pp is held at logic high until just be- fore ale/prog is to be pulsed. then ea /v pp is raised to v pp , ale/prog is pulsed low, and then ea /v pp is returned to a valid high voltage. the volt- age on the ea /v pp pin must be at the valid ea /v pp high level before a verify is attempted. waveforms and detailed timing specifications are shown in later sections of this data sheet. note: # ea /v pp pin must not be allowed to go above the maximum specified v pp level for any amount of time. even a narrow glitch above that voltage lev- el can cause permanent damage to the device. the v pp source should be well regulated and free of glitches. table 3. otp rom programming modes (h e 2.7v to 3.6v; h1 e 5v g 10%) mode rst psen ale/ ea / p2.6 p2.7 p3.3 p3.6 p3.7 v cc prog v pp program code data h1 l ? 12.75v l h1 h1 h1 h1 h1 verify code data h l h h l l l h h h program encryption h1 l ? 12.75v l h1 h1 l h1 h1 array address 0 3fh program lock bit 1 h1 l ? 12.75v h1 h1 h1 h1 h1 h1 bits bit 2 h1 l ? 12.75v h1 h1 h1 l l h1 bit 3 h1 l ? 12.75v h1 l h1 h1 l h1 read signature byte h l h h l l l l l h 272356 18 * see table 2 for proper input on these pins figure 10. programming the otp rom 16
8xl51fa/fb/fc programming algorithm refer to table 3 and figures 10 and 11 for address, data, and control signals set up. to program the 87l51fx the following sequence must be exercised. 1. input the valid address on the address lines. 2. input the appropriate data byte on the data lines. 3. activate the correct combination of control sig- nals. 4. raise ea /v pp from v cc to 12.75v g 0.25v. 5. pulse, ale/prog 5 times for the otp rom array, and 25 times for the encryption table and the lock bits. repeat 1 through 5 changing the address and data for the entire array or until the end of the object file is reached. program verify program verify may be done after each byte or block of bytes is programmed. in either case a complete verify of the programmed array will ensure reliable programming of the 87l51fx. the lock bits cannot be directly verified. verification of the lock bits is done by observing that their fea- tures are enabled. 272356 19 figure 11. programming signals waveforms rom and otp rom lock system the 87l51fx program lock system, when pro- grammed, protects the onboard program against software piracy. the 83l51fx has a one-level program lock system and a 64-byte encryption table. see line 2 of table 4. if program protection is desired, the user submits the encryption table with their code, and both the lock-bit and encryption array are programmed by the factory. the encryption array is not available without the lock bit. for the lock bit to be programmed, the user must submit an encryption table. the 87l51fx has a 3-level program lock system and a 64-byte encryption array. since this is an otp rom device, all locations are user-programmable. see table 4. encryption array within the otp rom array are 64 bytes of encryp- tion array that are initially unprogrammed (all 1's). every time that a byte is addressed during a verify, 6 address lines are used to select a byte of the en- cryption array. this byte is then exclusive-nor'ed (xnor) with the code byte, creating an encryption verify byte. the algorithm, with the array in the un- programmed state (all 1's), will return the code in its original, unmodified form. for programming the en- cryption array, refer to table 3 (programming the otp rom). when using the encryption array, one important fac- tor needs to be considered. if a code byte has the value 0ffh, verifying the byte will produce the en- cryption byte value. lf a large block ( l 64 bytes) of code is left unprogrammed, a verification routine will display the contents of the encryption array. for this reason all unused code bytes should be pro- grammed with some value other than 0ffh, and not all of them the same value. this will ensure maxi- mum program protection. 17
8xl51fa/fb/fc table 4. program lock bits and the features program lock bits protection type lb1 lb2 lb3 1 u u u no program lock features enabled. (code verify will still be encrypted by the encryption array if programmed.) 2 p u u movc instructions executed from external program memory are disabled from fetching code bytes from internal memory, ea is sampled and latched on reset, and further programming of the otp rom is disabled. 3 p p u same as 2, also verify is disabled. 4 p p p same as 3, also external execution is disabled. any other combination of the lock bits is not defined. program lock bits the 87l51fx has 3 programmable lock bits that when programmed according to table 4 will provide different levels of protection for the on-chip code and data. reading the signature bytes the 87l51fx/83l51fx has 3 signature bytes in lo- cations 30h, 31h, and 60h. to read these bytes fol- low the procedure for otp rom verify, but activate the control lines provided in table 3 for read signa- ture byte. location device contents 30h all 89h 31h all 58h 60h 83L51FA 70h 87l51fa f0h 83l51fb 71h 87l51fb f1h 83l51fc 72h 87l51fc f2h 18
8xl51fa/fb/fc otp rom programming and verification characteristics (t a e 21 cto27 c; v cc e 2.7v to 3.6v; v ss e 0v) symbol parameter min max units v pp programming supply voltage 12.5 13.0 v i pp programming supply current 75 ma 1/tclcl oscillator frequency 4 6 mhz tavgl address setup to prog low 48tclcl tghax address hold after prog 48tclcl tdvgl data setup to prog low 48tclcl tghdx data hold after prog 48tclcl tehsh p2.7 (enable) high to v pp 48tclcl tshgl v pp setup to prog low 10 m s tghsl v pp hold after prog 10 m s tglgh prog width 90 100 m s tavqv address to data valid 48tclcl telqv enable low to data valid 48tclcl tehqz data float after enable 0 48tclcl tghgl prog high to prog low 10 m s otp rom programming and verification waveforms 272356 20 note: * 5 pulses for the otp rom array, 25 pulses for the encryption table and lock bits. 19
8xl51fa/fb/fc thermal impedance the thermal impedance data is approximate for stat- ic air conditions at 1w of power dissipation. values will change depending on operating conditionis and applications. see the intel packaging handbook (or- der number 240800) for a description of intel's ther- mal impedance test methodology. package i ja i jc device n46 c/w 16 c/w all s87 cw 18 c/w 52 96 c/w 24 c/w 54 90 c/w 22 c/w 58 data sheet revision history this 8xl51fa/fb/fc data sheet (advanced infor- mation) replaces 272356-001 (product preview). 20

▲Up To Search▲

Price & Availability of 83L51FA

	To Download 83L51FA Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .